Week 7 — Semiconductor Devices: Diodes, BJTs, MOSFETs, and Op-Amps

Overview

Everything so far has been linear: doubling the input doubles the output, and superposition holds. Microelectronics begins where linearity ends. A diode conducts in one direction and blocks the other; a transistor uses a small signal to control a large one; an op-amp packages a huge gain into a part you can tame with feedback. These nonlinear and active devices are what make electronics do things — rectify, switch, amplify, compute — rather than just filter and divide. This is the densest week of the course because it introduces three device families and the single most important building block in analog design, the operational amplifier.

The unifying analytical trick is the operating point plus small-signal model: a nonlinear device is biased to a DC operating point, and small signals around that point see a linearized model (a resistance, a transconductance) to which all of Weeks 2–6 applies again. That is how we keep using linear circuit theory in a nonlinear world. For the op-amp, the complementary trick is the virtual short under negative feedback, which makes inverting/non-inverting amplifiers, integrators, and active filters fall out in one or two lines of algebra.

On the bench you will measure a diode’s I–V curve, build a rectifier, use a transistor as both a switch and a small-signal amplifier, and build the canonical op-amp circuits — including a buffer that finally fixes the divider-loading problem from Week 2 and an active filter that improves on Week 6’s passive one. This week rests on all prior weeks (biasing is DC analysis, signals are AC analysis, filters reuse Week 6) and feeds the signal-conditioning front ends of Weeks 9–10 and the embedded sensor work of Courses 1 and 4.

Readings

PEI Ch. 4: Semiconductor physics lite, diodes (rectifier, Zener, LED), bipolar junction transistors (biasing, common-emitter amplifier, switch), and MOSFETs (enhancement-mode, switching, logic). Extract: practical device behavior, biasing recipes, and failure modes.
PEI (op-amp chapter): The op-amp golden rules, inverting/non-inverting/summing/difference amplifiers, integrator/differentiator, comparators, and active filters. Extract: the configurations and their gain formulas.
CAD Ch. 4: The ideal op-amp model and feedback analysis — inverting, non-inverting, summing, difference, integrator, differentiator, with rigorous derivations. Plus CAD’s diode/transistor treatment for the device equations. Extract: the virtual-short method and clean derivations.
ME (transistor and chip experiments): Hands-on transistor switching and chip projects. Extract: build intuition and debugging habits for active circuits.

Key Concepts

The diode: a nonlinear element

The ideal-diode equation (Shockley):

\[ i_D = I_S\left(e^{v_D/nV_T}-1\right),\qquad V_T=\frac{kT}{q}\approx 25.85\ \text{mV at }300\,\text{K}. \]

Forward-biased it conducts with a roughly constant drop (~0.7 V for silicon, ~1.8–3 V for LEDs depending on color); reverse-biased it blocks until breakdown. For analysis we use models of increasing fidelity: ideal switch → constant-drop (0.7 V) → constant-drop + series resistance → full exponential. Applications: rectification (AC→DC), clamping/protection, the Zener as a voltage reference (operated in reverse breakdown), and the LED.

Operating point and small-signal linearization

A nonlinear device biased at a DC operating point \((V_D, I_D)\) presents, to small signals, a linear incremental model. For the diode, the small-signal resistance is

\[ r_d = \left.\frac{dv_D}{di_D}\right|_{Q} = \frac{nV_T}{I_D}. \]

This “linearize around the bias point” idea is the central method of analog design: choose a DC operating point with the DC analysis tools (Week 2), then analyze the signal with the linear small-signal model (Weeks 2–6 again). Get the bias wrong and the signal clips or the device saturates.

BJT and MOSFET as amplifier and switch

A BJT in active mode has collector current \(i_C=I_S e^{v_{BE}/V_T}\) and \(i_C=\beta i_B\); its small-signal transconductance is \(g_m=I_C/V_T\). As a switch it is driven between cutoff (off) and saturation (hard on). A MOSFET in saturation has \(i_D=\tfrac12 k(v_{GS}-V_{th})^2\) with \(g_m=k(v_{GS}-V_{th})\); as a switch it is voltage-controlled with very high input impedance and an on-resistance \(R_{DS(on)}\). The common-emitter / common-source amplifier gives voltage gain \(\approx -g_m R_C\); the transistor switch is the basis of digital logic and of driving loads (LEDs, relays, motors) from a logic pin — directly relevant to interfacing the Jetson’s GPIO.

The operational amplifier and the two golden rules

An ideal op-amp has infinite open-loop gain, infinite input impedance, zero output impedance, and infinite bandwidth. Under negative feedback, two golden rules make analysis trivial:

No current flows into the inputs (infinite input impedance).
The two inputs are at the same voltage — the virtual short — because infinite gain drives the differential input to zero.

From these, the standard circuits drop out immediately:

\[ \text{Inverting: } v_o=-\frac{R_f}{R_1}v_i,\qquad \text{Non-inverting: } v_o=\left(1+\frac{R_f}{R_1}\right)v_i,\qquad \text{Buffer: } v_o=v_i. \]

The integrator (\(v_o=-\frac{1}{RC}\int v_i\,dt\)) and differentiator (\(v_o=-RC\,dv_i/dt\)) realize the calculus operations directly in hardware — the same operations the capacitor performs, now with gain and a low-output-impedance drive. The buffer (unity-gain follower) has near-infinite input and near-zero output impedance: it is exactly the fix for Week 2’s divider-loading problem.

Real op-amp limits

The ideal model breaks at the edges: finite gain–bandwidth product (gain rolls off with frequency), slew-rate limiting (max \(dv/dt\) on the output), input offset voltage and bias currents, finite output swing (rail limits), and saturation. Knowing these prevents the classic surprises — a “DC-correct” amplifier that distorts fast signals (slew/bandwidth) or sits stuck at a rail (saturation/offset).

Active filters (closing Week 6)

With the op-amp, build a Sallen–Key or multiple-feedback active filter: a second-order low/high/band-pass with buffered output, settable gain, and no inductor. Compare its measured Bode plot to the passive RLC of Week 6 — the active version doesn’t load, holds its \(Q\), and is far easier to cascade.

Theory Exercises

From the Shockley equation derive the small-signal diode resistance \(r_d=nV_T/I_D\). Compute \(r_d\) at \(I_D=1\) mA.
Design an LED current-limiting resistor for 5 V supply, \(V_{LED}=2.0\) V, \(I_{LED}=10\) mA, and state the resistor power dissipation.
Analyze a half-wave and a full-wave (bridge) rectifier; sketch input and output, and size a smoothing capacitor for a target ripple voltage given load current and frequency.
For a common-emitter amplifier, derive the small-signal voltage gain \(A_v\approx -g_m R_C\) with \(g_m=I_C/V_T\); design the bias for a chosen quiescent \(I_C\).
Using the two golden rules, derive the inverting and non-inverting gain formulas and the integrator relation \(v_o=-\frac1{RC}\int v_i\,dt\).
Explain why a unity-gain buffer solves the Week-2 divider-loading problem, in terms of input/output impedance.
Derive the cutoff and \(Q\) of a Sallen–Key low-pass in terms of its R’s and C’s.

Lab / Bench Work

Diode I–V curve: Sweep voltage across a diode (series resistor + variable supply / potentiometer), measure \(v_D\) and \(i_D\) with the Fluke, and plot the I–V curve. Extract the ~0.7 V knee; repeat with an LED and note the higher, color-dependent drop.

Rectifier: Build a half-wave then a bridge rectifier from a sine source; capture the output on the scope. Add a smoothing capacitor and measure ripple vs the predicted value; vary load and observe ripple change.

Transistor switch & amplifier: (1) Use a BJT or MOSFET to switch an LED/load from a logic-level input — the pattern for driving loads from the Jetson’s 3.3 V GPIO (use the logic level converter where 5 V logic is involved). (2) Build a common-emitter amplifier, bias it, and measure the small-signal voltage gain with a small sine input; confirm clipping when input is too large (bias/headroom lesson).

Op-amp circuits: Build inverting and non-inverting amplifiers; measure gain vs the resistor-ratio prediction. Build a unity-gain buffer and demonstrate the Week-2 fix: drive a heavy load through a divider with and without the buffer. Build an integrator and feed it a square wave (expect a triangle output). Build a Sallen–Key active low-pass and measure its Bode plot; compare to the passive RLC from Week 6.

Qucs-S (ngspice): Simulate each circuit (use real device models where available) and reconcile with measurements, especially the rectifier ripple and amplifier gain/clipping.

Measurement Methodology

Bias first, signal second: verify the DC operating point with the Fluke before applying any signal; a wrong bias point invalidates the small-signal measurement.
Watch the rails: op-amp output can’t exceed its supply (and many can’t reach it — note the rail-to-rail spec); apparent “gain error” is often saturation. Keep input amplitudes small enough to stay linear.
Slew/bandwidth: at higher frequencies, a triangular or distorted output of a sine indicates slew-rate limiting — measure the max \(dv/dt\) and compare to the datasheet slew rate.
Decoupling: place a small ceramic (Week 3) across the op-amp/transistor supply pins; without it, active circuits oscillate or pick up noise. This is a real, observable effect on the scope.
Reconcile: device curves, gains, and ripple vs hand calculation and Qucs-S. Attribute residuals to device tolerance, \(\beta\)/\(V_{th}\) spread, and the simplified models.

Expected baselines: Silicon diode knee ~0.6–0.7 V; LED drop 1.8–3.3 V by color. Op-amp gains within a few percent of the resistor ratio (limited by resistor tolerance, not the op-amp, at low frequency). Buffer demonstrably removes divider sag. Active filter holds its passband gain and \(Q\) where the passive one drooped under load.

Connections

The small-signal/operating-point method is the analog-design backbone and reappears wherever a device is biased and driven. The op-amp buffer closes the loop on Week 2’s loading problem; the integrator/differentiator are the calculus operations of Weeks 3–4 in active form. The active filter extends Week 6 and becomes the practical anti-alias and reconstruction filter of Week 9. Transistor switching and logic-level interfacing are exactly how the Jetson’s GPIO drives real loads and reads 5 V logic safely (the level converters), connecting to Courses 1 and 4. Op-amp signal conditioning (gain + filtering) is the standard front end before the ADC in Weeks 9–10.