Module 6 Exercises — The Cortex-M Bridge
Back to the Course 3 syllabus. Read first: Yiu 3–7 core; 8, 10.1–10.4, 12, 13, 20, 21 as assigned.
Work in course3/m6/ of the labs repo. Everything here runs on the Mac: the arm-none-eabi cross-toolchain from the Course 2 firmware setup compiles and disassembles Cortex-M4 code without a board. The NUCLEO stays in its drawer — this module is about reading the M-profile world with A64 eyes.
Exercises
Exercise 6.1 — One routine, two ISAs. Cross-compile Module 5’s naive C dot product for the Cortex-M4 (arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -O2 -c) and disassemble with arm-none-eabi-objdump -d. Put it side by side with the A64 -O2 disassembly from Exercise 5.2 and complete the comparison table (finishing what Exercise 2.2 started on paper):
| Axis | Cortex-M4 (T32) | Apple Silicon (A64) |
|---|---|---|
| Instruction count (inner loop) | … | … |
| Code bytes (whole routine) | … | … |
| Encoding widths used | … | … |
| Registers touched | … | … |
| FP/SIMD instructions used | … | … |
Exercise 6.2 — AAPCS, M-profile edition. Write a small Thumb-2 leaf function per the 32-bit AAPCS (arguments in r0–r3, result in r0) — on paper first, then check yourself by compiling the equivalent C and diffing your hand version against GCC’s output. In notes.md, tabulate the calling-convention differences against Module 4: argument registers, callee-saved set, link register behavior, stack alignment (8 vs. 16).
Exercise 6.3 — Exception entry, on paper. Yiu 7–8’s core mechanism, traced by hand: an interrupt fires while a function is using r0–r3, r12, and the FPU. Draw the exact stacked frame the hardware pushes (with and without lazy FP stacking), state what lands in LR (EXC_RETURN) and how the return-from-exception works. Then write the A-profile contrast paragraph: what Apple/A-profile cores do instead (vector table vs. exception levels, banked registers, who saves what). Deliverable: the two annotated diagrams plus the contrast note.
Exercise 6.4 — Read a real vector table. Open the Course 2 labs repo’s STM32 startup file (firmware/ modules) and annotate, line by line in notes.md: the initial SP entry, the reset vector, the .data copy and .bss zeroing loops, the call into main, and where the NVIC vectors for the Course 2 peripherals (ADC, DMA, TIM) sit. Cross-reference each piece to Yiu 7.5 and the STM32L476 reference manual’s vector table.
Exercise 6.5 — CMSIS-DSP, read against your NEON. Read the CMSIS-DSP source of arm_dot_prod_q15 (it ships in the Course 2 firmware tree). Identify the SIMD-within-a-register tricks (SMLALD on packed 16-bit pairs) and map each to its Module 5 counterpart (SQDMULH, FMLA). In notes.md: two columns, “M4 DSP extension” vs. “A64/NEON equivalent,” for every instruction in the inner loop. This closes the loop with Yiu 21–22 and is the literal code Course 2’s filter labs call.
Exercise 6.6 — Capstone: One Algorithm, Two ARMs. The course deliverable: a 1–2 page staff-level note reconciling the same dot product on the two machines, across every layer this course covered — ISA and encodings (6.1), calling convention (6.2), pipeline and ILP (2.6 vs. the M4’s in-order 3-stage), memory system (2.4 vs. flash wait states and the M4’s SRAM), floating point and saturation (5.2–5.4 vs. 6.5), and interrupt model (6.3 — what happens to each machine’s state when the ADC fires mid-loop). Close with the engineering judgment paragraph: which classes of DSP work belong on which core, and why — the question Course 2’s Module 8.5 benchmark answers empirically.